1. Field of the Invention
The present invention generally relates to an integrated circuit provided with a memory unit main body such as a dynamic random access memory (DRAM) and, more particularly, to improvement in efficiency of a test of a memory unit main body in a semiconductor circuit.
2. Description of the Related Art
FIG. 9 shows a circuit construction of a memory circuit in a memory unit main body such as a dynamic random access memory (DRAM). The memory circuit is capable of outputting (x+1)-bit data simultaneously. The memory unit main body is provided with a total of (p+1) memory circuits for each address. x and p indicate positive integers.
Referring to FIG. 9, the memory unit main body comprises bit line pairs 30 to each of which a plurality of memory elements are connected so that one of the plurality of memory elements is selected for connection by a row address; memory blocks 31 provided with a total of (x+1) bit line pairs 30; a redundant memory block 32 for a recovering purpose provided with a total of (x+1) bit line pairs 30; a total of (x+1) local I/O line pairs 33 each connecting the plurality of memory blocks 31 and 32; a total of (x+1) global line pairs 34 each connected to a respective one of the local I/O line pairs 33; a total of (x+1) output amplifier circuits 35 each connecting the selected memory element with an internal address bus of an integrated circuit; output signal line pairs 36 each connected to a respective one of the output amplifying circuits 35; bit line pair connection switches 37 each provided in a respective one of the memory blocks 31 or the redundant memory block 32 so as to connect a respective one of the bit line pairs 30 to a respective one of the local I/O line pairs 33 in accordance with a column line selection signal generated based on a column address; global I/O line pair connection switches 38 for connecting a respective one of the global I/O line pairs 34 to a respective one of the output signal line pairs 36 in accordance with a global I/O enable signal generated based on a column address.
The memory unit main body is constructed such that a row address is strobed by a row address strobe signal so as to connect a plurality of memory elements in the memory blocks 31 associated with the same row address with the respective bit line pairs 30. The column address is strobed by the column address strobe signal, whereupon a column line selection signal and a global I/O enable signal are generated based on the column address so that one of the memory blocks 31 is connected to the corresponding local I/O line pair 33 and one of the global I/O line pairs 34 is connected to the corresponding output signal line pair 36. This way, data corresponding to the contents of the (x+1) memory elements in the memory block 31 are output from the output amplifying circuit 35.
FIG. 10 is a block diagram showing a construction of a memory unit provided with the memory unit main body as described above. The memory unit is used together with a function unit (not shown) so as to form an integral part in an integrated circuit. Data is exchanged between the memory unit and the function unit via a bus with an (mxc3x97n))-bit width. In a test mode of the memory unit, m-bit data is input and output between a tester and the memory unit.
Referring to FIG. 10, the memory unit comprises: a memory unit main body 39; an internal data bus 40 having an (mxc3x97n))-bit width and used for data exchange between the memory unit 39 and a function unit (not shown); a flip-flop 41 receiving a test data write clock signal and m-bit test write data and causing, in a test mode, each data latched by the test data write clock signal to branch to n individual signal lines so as to output the (mxc3x97n)-bit signal to the internal data bus 40; an address bus 42; a test row address strobe signal line 43; a test column address strobe signal line 44; a test write enable signal line 45; a q(=log2n)-bit test data selection signal line 46; and a data multiplexer 47 connected to the internal data bus 40 and selecting m-bit data in accordance with a binary value occurring on the test data selection signal line 46 for output to an external unit. The memory unit main body 39 also selects m-bit data on the internal data bus 40 in accordance with the binary value occurring on the data selection signal line 46 so as to write or read the m-bit data.
A description will now be given of the operation according to the related art.
In a test mode, m-bit data output from a tester is latched by the D flip-flop 41. The (mxc3x97n)-bit resulting from the branching of the latched data to the n individual signal lines is output to the internal data bus 40. The row address is set in the address bus 42 and the test write enable signal line 45 is brought to a write enable level. In this state, the test row address strobe signal is asserted so that the road address is set. Further, the column address is set in the address bus 42 and a predetermined binary value is set in the data selection signal line 46. In this state, the test column address strobe signal is asserted. With this, data is written in the m memory elements corresponding to the binary value. By changing the binary value a total of n times by incrementing it from xe2x80x9c00 . . . 00xe2x80x9d to xe2x80x9c11 . . . 11xe2x80x9d, data is written in a total of (mxc3x97n)) memory elements corresponding to an addresses comprising the row address and the column address. By repeating this procedure for the entirety of the addresses, data is written in all of the memory elements.
Subsequently, by setting a row address and a column address in the memory unit main body 39 using a similar procedure, the data in the (mxc3x97n) memory elements are output to the internal bus 40. By changing the level occurring on the test data selection signal line 46 a total of n times by incrementing it from xe2x80x9c00 . . . 00xe2x80x9d to xe2x80x9c11 . . . 11xe2x80x9d, data is read out from the (mxc3x97n) memory elements corresponding to an address. By repeating the procedure for the entirety of the addresses, data is read out from all of the memory elements.
When it is found that the read data matches the written data, a determination is made that the memory block 31 is not defective. When it is determined that the data do not match, a determination is made that the memory block 31 that caused a mismatch is defective. A recovery code is then output so as to use the redundant memory block 32 in place of the defective memory block 31.
Since the integrated circuit according to the invention is constructed as described above, a write process and a read process are performed in a memory element a relatively large number of times. Thus, an enormous amount of time is required to test the memory unit.
With the high-integration large-capacity memory units that are built recently, the time required for a memory test is increased so significantly that the productivity suffers.
For example, if the integrated circuit as described above is provided with a 256-bit wide internal data bus and configured to receive 8-bit write data and output 8-bit readout data, a write process and a read process should be repeated for total of 32 (n=256/8=32) times for memory elements corresponding to a given address.
Accordingly, a general object of the present invention is to provide an integrated circuit in which the aforementioned problem is eliminated.
Another and more specific object of the present invention is to provide an integrated circuit in which a write process and a read process are performed efficiently by taking advantage of the memory construction inherent in the memory unit, and in which it is possible to conduct a memory test and to generate a recovery code more efficiently and in a shorter period of time than in the integrated circuit provided with the memory unit according to the related art described above.
Still another object of the present invention is to provide an integrated circuit in which the aforementioned objects can be achieved without increasing the number of terminals used in the test mode, that is, by using a limited number of input and output terminals provided in the integrated circuit.
The aforementioned objects can be achieved by an integrated circuit comprising: a D flip-flop receiving m-bit write data and a clock signal, causing the m-bit data latched by the clock signal to branch to n individual signal lines and outputting the resultant (mxc3x97n)-bit data; and a plurality of memory circuits provided with a plurality of memory blocks including a recovery memory block and configured to input and output (x+1)-bit data simultaneously; and a write control circuit receiving, m-bit parallel, the (mxc3x97n)-bit data output from the D flip-flop, receiving a q-bit data selection signal and writing, in accordance with a binary value indicated by the q-bit data selection signal, the output data from the D flip flop to the plurality of memory circuits in units of integral multiplex of (x+1) bits in a total of 2q operations, where m, n, x, and q indicate positive integers, (x+1) greater than m and n greater than 2q.
The integrated circuit may further comprise: a match determination circuit subjecting the multiples-of-(x+1)-bit data output from each of the plurality of memory circuits to determination on a match and outputting results of the determination; a determination result output circuit receiving results of the determination from the match determination circuit, receiving the q-bit data selection signal and outputting match determination data indicating a data mismatch occurring in the match determination circuit in accordance the binary value indicated by the data selection signal.
The integrated circuit may further comprise: a tristate buffer receiving the readout data from the plurality of memory circuits and receiving, as a control signal, the output from the determination result output circuit.
The integrated circuit may further comprise: encoders each provided for a corresponding memory circuit in which the same data is written, so as to encode data input to the corresponding memory circuit; and decoders each provided for a corresponding memory circuit in which the same data is written, so as to encode data output the corresponding memory circuit.
The encoders and decoders may be operated in accordance with an address.